Home / Technology / AMD outlines its future: 7nm GPUs with PCIe 4, Zen 2, Zen 3, Zen 4

AMD outlines its future: 7nm GPUs with PCIe 4, Zen 2, Zen 3, Zen 4

  AMD Radeon Instinct MI60.
Enlarge / AMD Radeon Instinct MI60.

AMD today announced its plans for the next years of product development with a range of new CPUs and GPUs in the development pipeline.

The front of the GPU features two new data center-centric GPUs: the Radeon Instinct MI60 and MI50. Based on the Vega architecture and the TSMC 7nm process, the cards are not primarily based on graphics cards (regardless of what might be called GPUs), but rather on machine learning, high performance computing, and rendering applications , [1

9659004] MI60 ships with 32GB of ECC HBM2 (second generation high-bandwidth memory), while the MI50 gets 16GB, and both have memory bandwidths of up to 1TB / s. ECC is also used to protect the entire internal memory of the GPUs themselves. The cards also support PCIe 4.0 (which doubles the transfer speed of PCIe 3.0) and direct GPU-to-GPU connections with AMD's Infinity Fabric. This provides bandwidth of up to 200 GB / s (three times more than PCIe 4) for up to 4 GPUs.

The maps support a variety of data types for the calculation; For neural networks and machine learning, there is support for 16-bit half-precision floating-point numbers with 4-bit and 8-bit integer support. For HPC workloads, there are floating-point numbers with single (32-bit) and double (64-bit) precision. AMD claims that the MI60 will be the fastest dual-precision accelerator at up to 7.4 TFLOPS, the MI50 at 6.7 TFLOPS.

The cards also provide built-in support for virtualization, so one card can be securely shared between multiple virtual machines. This makes it easier for cloud operators to offer GPU-accelerated virtual machines.

The MI60 will be delivered to customers in the data center by the end of the year. MI50 comes a little later, but should be available by the end of Q1 2019.

On the CPU side of things, AMD talked in detail about the upcoming Zen 2 architecture. The goal of the original Zen architecture was to compete with AMD at least what Intel had to offer. AMD knew that Zen would not take advantage of Intel's performance advantage, but the pricing and features of its chips still made it attractive, especially for workloads that showed certain shortcomings of Intel parts (fewer memory channels, less I / O bandwidth). Zen 2 promises not only to be competitive with Intel, but to be superior to it.

  TSMC's 7 nm process gives AMD the advantage of manufacturing over Intel. "Src =" https://cdn.arstechnica.net/wp-content/uploads/ 2018/11/7nm-leapfrog-640x284.png "width =" 640 "height =" 284 "srcset =" https: // cdn .arstechnica.net / wp-content / uploads / 2018/11 / 7nm-leapfrog.png 2x
Enlarge / TSMC's 7-nm process gives AMD the manufacturing advantage over Intel.


The key to this is the 7nm process used by TSMC, which provides the double transistor density of the 14nm process Zen parts. At the same level of performance, the performance is reduced by about 50 percent, or with the same power consumption, the performance is increased by about 25 percent. TSMC's 14nm and 12nm processes are behind Intel's 14nm process in terms of power per watt, but TSMC will take the lead at 7nm.

Zen 2 will also address some weak aspects of the original Zen. For example, the original Zen used 128-bit data paths to perform 256-bit AVX2 operations. Each operation was divided into two parts and processed one after the other. For workloads with AVX2, Intel has a great advantage with its native 256-bit implementation. Zen 2 doubles the floating point execution units and data paths to 256 bits, doubling the available bandwidth and greatly improving the performance of this code. For integer workloads, branch prediction and prefetching have been refined and some caches expanded.

Zen 2 also offers improved hardware protection against some variations of Specter attacks.

The original Zen used a multichip module design. Chips that used one, two, or four chips (for Ryzen, first-generation thread ripper, or epyc / second-generation thread ripper) all packaged in one package. Each chip had two core complexes (four-core blocks), two memory controllers, some Infinity Fabric connections (for connections between chips), and some PCIe channels. This made it easy for AMD to scale from the single-die-8-core / 16-thread Ryzen to the 32-core / 64-thread epyc.

  The original Zen topology: Each chip has all the necessary parts a complete processor. "src =" https://cdn.arstechnica.net/wp-content/uploads/2018/11/zen-topology.png "width =" 457 "height =" 417

The original Zen topology: Everyone The has all the parts needed for a complete processor.


Zen 2 takes a very different approach, albeit still a multi-chip design. Instead of each chip containing CPUs, memory controllers and I / O, the different roles are split into the new design. There will be a single 14nm I / O with eight storage controllers, eight Infinity Fabric ports and PCIe lanes, and a number of 7nm "chipsets" containing only CPUs and Infinity Fabric. This new approach was intended to eliminate some of the more awkward aspects of the original Zen. For example, there is a significant latency overhead when one core of a Zen chip needs to use memory from another chip. With the Zen-2 design, the memory latency should become much more consistent.

  The new Zen 2 design: The 14 nm I / O chips are covered with standard I / O functions, with the 7 nm "chiplets" containing only CPUs. "Src =" https://cdn.arstechnica.net/wp-content/uploads/2018/11/zen-2-topology.png "width =" 514 "height =" 404

The new Zen 2 design : common I On the 14nm I / O die are / O functions, with the 7nm "chiplets" containing only CPUs.


AMD says Zen 2 is now scanning, with processors expected to hit the market in 2019. Zen 3 with an improved version of the 7nm process is currently "on track" and is expected to land in 2020, and Zen 4 is in a more advanced design stage process.

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