Video: New arm processors for mobile devices tailored to AI and VR.
The chip designer arm has introduced the Cortex-A76 CPU and promises 35 percent more power than its predecessor. Arm announced Thursday the new chip and announced tremendous performance improvements for Windows 10 on arm laptops and Android smartphones when the Cortex-A76 CPU 2019 came on the market.
Arm introduces the new CPU with "laptop class" performance combined with mobile efficiency. Intel and AMD's survey finds that laptops have averaged single-digit performance improvements in recent years compared to their 35 percent jump last year. Arm also says the new chip will deliver 40 percent better energy efficiency and a fourfold improvement in machine learning performance.
A more powerful arm CPU would be an important reinforcement for Microsoft and its current Windows 1
Qualcomm's arm-based Snapdragon 835 has helped these notebooks deliver mobile battery life and 4G connectivity. However, previous tests have found that their performance is comparable to Intel's low-end chips, which are found in much cheaper notebooks.
The cheapest Windows 10 on arm laptop is $ 599. ZDNet's sister site CNET's review of HP's Envy x2 at $ 999 notes that slow performance leaves an otherwise solid mobile notebook in the lurch.
As CNET reports, Rene Haas, president of Arms' intellectual property group, said these new Arm-designed chips should compete with Intel's high-end Core i7 models.
Patrick Moorhead, an analyst at Moor Insights and Strategy, said that Arm's faster design is a "big deal," since it's Windows 10 PCs and Chromebooks.
Mike Filippo, chief designer of Arm, said the Cortex-A76 has about the same performance as Intel's Core i5-7300, but could be equipped with more cache memory could also compete with a Core i7.
Arm has described some of the key microarchitectural changes in the Cortex-A76, which Arm has implemented to improve performance.
"Cortex-A76 is Arm's first quad decoder kernel, which increases the maximum number of instructions per cycle, and up to eight operations per cycle can then be sent to the out-of-order core, thereby supporting greater area / power will be -optimized instruction window, "he notes.
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